In its basic form, a field-effect transistor (FET) includes a source region, a drain region and a channel between the source and drain regions. A gate regulates electron flow through the channel between the source and drain regions.
Due to their superior electrostatics gate all around nanowire channel field effect transistors (e.g., nanowire FETs) are expected to enable density scaling beyond current planar CMOS technology. There are however notable challenges related to fabricating gate all around nanowire FETs, especially at scaled dimensions. For instance, to increase layout density, the nanowires are placed close together and/or are stacked. Forming a gate surrounding the nanowires in this case is challenging.
Thus, improved techniques for fabricating gate all around nanowire FETs would be desirable.